The present invention relates to a data processing device having a pipeline structure. Pipeline structures are well known, and used in microprocessors and microcontrollers. To work most efficiently, a pipeline is filled up with a sequence of instructions. Once the sequence is interrupted, the pipeline is filled up again. This causes a loss of processing speed for the microprocessor. Such interrupts occur mainly when a jump, branch or loop instruction is executed, because the following instruction is often not the instruction which follows the jump, branch or loop instruction.
Jump and branch instructions generally depend on a condition for its decision whether or not a jump or branch is to be executed. On the other hand, a loop instruction includes a parameter which indicates the number of times the loop is executed and a parameter which indicates the beginning of the loop. In particular, digital signal processors are often using loop instructions. Therefore, loop instructions can have an important influence on the resulting execution speed of a processor or a data processing unit. It is therefore an object of the present invention to provide a data processing device with means to execute loop instructions as fast as possible.